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EN0-001 Exam Dumps - ARM Accredited Engineer

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Question # 17

When using an Operating System, which instruction is used by user code to request a service from the kernel?

A.

BLX

B.

RFEFD

C.

SRSFD

D.

SVC

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Question # 18

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

A.

VA == PA; No address translations; instructions and data are not cached

B.

VA! = PA; No address translations; instructions may be cached but not data

C.

VA == PA; Address translations take place; data may be cached but not instructions

D.

VA == PA; No address translations; instructions may be cached but not data

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Question # 19

Before execution:

R0=0xFFFFFFFF

R1 = ?

EOR R0, R0, R1

If R0=0x00000000 after executing the EOR instruction above, what was the value in R1 before the instruction executed?

A.

0x00000000

B.

0xFFFFFFFF

C.

0x11111111

D.

0xAAAAAAAA

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Question # 20

The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.

In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?

Question # 21

A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.

When is this method INAPPROPRIATE?

A.

When executing the software using a simulation model

B.

When the processor is a Cortex-R4

C.

When instruction tracing is enabled

D.

When the processor is not executing instructions from cache

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Question # 22

The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?

A.

Translates virtual addresses to physical addresses

B.

Generates parity information to detect soft errors in memory

C.

Performs access permission checks

D.

Permits the system to be divided into secure and normal worlds, through the use of ARM's TrustZone technology

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Question # 23

An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.

STR r0, [r1] ; write to interrupt controller register to clear interrupt request

CPSIE i ; re-enable IRQ interrupts

Which of the following instructions should be placed at position in order to ensure that the interrupt controller sees the write before interrupts are re-enabled?

A.

DMB

B.

DSB

C.

ISB

D.

NOP

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Question # 24

Which of the following pairs of statements about the difference between a Memory Management Unit (MMU) and a Memory Protection Unit (MPU) is correct?

A.

The MMU uses translation tables. The MPU does not use translation tables.

B.

The MMU uses only physical addresses. The MPU translates virtual addresses to physical addresses.

C.

The MMU defines cacheability attributes for memory. The MPU does not define cacheability attributes for memory.

D.

The MMU defines access permissions for memory. The MPU does not define access permissions for regions of memory.

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